1. Field of the Invention
The present invention relates to a multiprocessor system and, more particularly, to a multiprocessor system which conducts data transfer through a plurality of shared buses.
2. Description of the Related Art
As conventional multiprocessor systems of this kind, other than a multiprocessor system in which each processor element fixedly serves as a master or a slave, there are multiprocessor systems in which each processor element is dynamically operable as a master or a slave, so that message transfer between processor elements and input/output transfer between a processor element and an input/output device are respectively conducted by using a plurality of shared buses in order to efficiently execute data transfer between the processor elements.
FIG. 24, for example, is a block diagram showing an example of a structure of this conventional multiprocessor system (see Japanese Patent Laying-Open (Kokai) No. Heisei 5-6333).
The conventional multiprocessor system includes a plurality of processors 12-1 and 12-2 and a plurality of bus controllers 13-1 and 13-2 which respectively form processor elements, and a plurality of input/output devices 16-1, 16-2 and 16-3 and a plurality of adaptors 15-1 and 15-2, with the plurality of processors 12-1, 12-2 connected to a plurality of shared buses 14-1, 14-2 through the plurality of bus controllers 13-1 and 13-2 and with the plurality of input/output devices 16-1, 16-2 and 16-3 connected to the plurality of shared buses 14-1 and 14-2 through the plurality of adaptors 15-1 and 15-2.
Each of the plurality of processors 12-1 and 12-2 includes an input/output processing unit and a message communication processing unit as a kernel processing unit of an operating system.
In response to an input/output request to the input/output devices 16-1, 16-2 and 16-3, the input/output processing device hands over address information and transfer data information of the input/output device to the bus controllers 13-1 and 13-2 to respectively activate input/output. Then, when input/output is completed, the unit receives an interruption notification from the bus controllers 13-1 and 13-2 to notify a program having issued the input/output request of the completion.
Upon receiving a request for data communication between processors, the message communication processing unit hands over address and transfer data information of a requesting processor to the bus controllers 13-1 and 13-2 to make a data transmission request. In reception processing, when data transmission is made from other processor, the unit receives an interruption notification from the bus controllers 13-1 and 13-2 to receive data and hands over the data to a requesting source program.
In this conventional multiprocessor system, each processor element serves as a master or a slave to conduct input/output transfer to/from the input/output device and message transfer between the processor elements by using the plurality of shared buses 14-1 and 14-2. Since one bus can be commonly used for input/output transfer and message transfer, a plurality of message transfers and a plurality of input/output transfers can be simultaneously conducted by using the plurality of shared bus according to a volume of data transferred between the processor elements and transfer traffic. Therefore, as long as the number of requests made simultaneously for data transfer including those for message transfer and for input/output transfer is not more than the number of shared buses, no processing will be kept waiting because of busyness of a bus.
In general, the following demands are made on a shared bus which conducts data transfer between a plurality of processor elements in a multiprocessor system.
(1) In terms of performance, to realize high-speed data transfer with a small circuit area and lower power consumption.
(2) In terms of easiness of expansion and reuse of resources, even when physical addition, modification or deletion is made of a processor element, to minimize design change of other processor element and a shared bus.
(3) In terms of easiness of verification, to selectively monitor conditions of data transfer between the processor elements and debug information of each processor element.
In the above-described conventional multiprocessor system, being separated from input/output transfer of the input/output device, message transfer between processor elements is conducted at a high speed without waiting for input/output transfer to end. When the volume of transfer data in message transfer between the processor elements is large, however, a time period where the shared bus is occupied is long to make message transfer between other processor elements wait, which causes a problem that high-speed data transfer between the processor elements is difficult as a whole of the system.
When the number of shared buses is increased in order to cope with this problem, another problem occurs that overhead in circuit scale will be enormous.
On the other hand, even when the volume of transferred data in message transfer between the processor elements is small, because it is necessary to generate an interruption to processing of an internal processor of a processor element and conduct interruption processing at each message transfer, efficiency of data transfer by the internal processor of the processor element will be relatively decreased.
Moreover, at the time of debugging of a program of the entire system or a processor element, it is impossible to selectively monitor conditions of data transfer between the processor elements and debug information of each processor element, so that debugging efficiency is low.
As a countermeasure against the problem, when a bus monitoring circuit or an address tracing function is mounted for each shared bus or processor element as disclosed in Japanese Patent Laying-Open (Kokai) NO. 2000-330877 or Japanese Patent Laying-Open (Kokai) No. Heisei 4-195552, for example, another problem occurs that overhead in circuit scale will be enormous.